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base repository: m-labs/artiq
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  • 4 commits
  • 8 files changed
  • 1 contributor

Commits on Dec 9, 2014

  1. pyon: unit support

    sbourdeauducq committed Dec 9, 2014
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    597fe57 View commit details
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  4. dds: fix phase modes

    sbourdeauducq committed Dec 9, 2014
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    059608d View commit details
Showing with 26 additions and 17 deletions.
  1. +1 −1 artiq/coredevice/core.py
  2. +5 −6 artiq/coredevice/dds.py
  3. +1 −1 artiq/coredevice/runtime.py
  4. +8 −0 artiq/management/pyon.py
  5. +0 −1 doc/manual/installing.rst
  6. +7 −6 soc/runtime/dds.c
  7. +1 −1 soc/runtime/dds.h
  8. +3 −1 test/serialization.py
2 changes: 1 addition & 1 deletion artiq/coredevice/core.py
Original file line number Diff line number Diff line change
@@ -57,7 +57,7 @@ def build(self):
self.ref_period = self.runtime_env.internal_ref_period
self.comm.switch_clock(False)
else:
self.ref_period = self.external_clock
self.ref_period = 1/self.external_clock
self.comm.switch_clock(True)
self.initial_time = int64(self.runtime_env.warmup_time/self.ref_period)

11 changes: 5 additions & 6 deletions artiq/coredevice/dds.py
Original file line number Diff line number Diff line change
@@ -100,15 +100,14 @@ def on(self, frequency, phase_mode=PHASE_MODE_DEFAULT, phase_offset=0):
# Use soft timing on FUD to prevent conflicts when reprogramming
# several channels that need to be turned on at the same time.
rt_fud = merge or self.previous_on
ftw = self.frequency_to_ftw(frequency)
if self.phase_mode != PHASE_MODE_CONTINUOUS:
phase_per_microcycle = ftw*int64(
self.dds_sysclk.amount*self.core.runtime_env.ref_period)
sysclk_per_microcycle = int(self.dds_sysclk*
self.core.ref_period)
else:
phase_per_microcycle = int64(0)
sysclk_per_microcycle = 0
syscall("dds_program", time_to_cycles(now()), self.reg_channel,
ftw, int(phase_offset*2**14),
phase_per_microcycle,
self.frequency_to_ftw(frequency), int(phase_offset*2**14),
sysclk_per_microcycle,
rt_fud, self.phase_mode == PHASE_MODE_TRACKING)
self.previous_frequency = frequency
self.sw.on()
2 changes: 1 addition & 1 deletion artiq/coredevice/runtime.py
Original file line number Diff line number Diff line change
@@ -20,7 +20,7 @@
"rtio_get": "iI:I",
"rtio_pileup_count": "i:i",
"dds_phase_clear_en": "ib:n",
"dds_program": "IiiiIbb:n",
"dds_program": "Iiiiibb:n",
}

_chr_to_type = {
8 changes: 8 additions & 0 deletions artiq/management/pyon.py
Original file line number Diff line number Diff line change
@@ -23,6 +23,8 @@

import numpy

from artiq.language.units import Quantity


_encode_map = {
type(None): "none",
@@ -34,6 +36,7 @@
list: "list",
dict: "dict",
Fraction: "fraction",
Quantity: "quantity",
numpy.ndarray: "nparray"
}

@@ -100,6 +103,10 @@ def encode_fraction(self, x):
return "Fraction({}, {})".format(encode(x.numerator),
encode(x.denominator))

def encode_quantity(self, x):
return "Quantity({}, {})".format(encode(x.amount),
encode(x.unit))

def encode_nparray(self, x):
r = "nparray("
r += encode(x.shape) + ", "
@@ -133,6 +140,7 @@ def _nparray(shape, dtype, data):
"true": True,

"Fraction": Fraction,
"Quantity": Quantity,
"nparray": _nparray
}

1 change: 0 additions & 1 deletion doc/manual/installing.rst
Original file line number Diff line number Diff line change
@@ -128,7 +128,6 @@ Installing the host-side software
$ git clone https://github.com/openrisc/llvm-or1k
$ cd ~/artiq-dev/llvm-or1k/tools
$ git clone https://github.com/openrisc/clang-or1k clang
$ cd ~/artiq-dev/llvm-or1k/tools/clang

$ cd ~/artiq-dev/llvm-or1k
$ mkdir build
13 changes: 7 additions & 6 deletions soc/runtime/dds.c
Original file line number Diff line number Diff line change
@@ -41,22 +41,22 @@ void dds_phase_clear_en(int channel, int phase_clear_en)

/*
* DDS phase modes:
* - continuous: Set phase_per_microcycle=0 to disable POW alteration.
* - continuous: Set sysclk_per_microcycle=0 to disable POW alteration.
* phase_tracking is ignored, set to 0.
* Disable phase accumulator clearing prior to programming.
* - absolute: Set phase_per_microcycle to its nominal value
* - absolute: Set sysclk_per_microcycle to its nominal value
* and phase_tracking=0.
* Enable phase accumulator clearing prior to programming.
* - tracking: Set phase_per_microcycle to its nominal value
* - tracking: Set sysclk_per_microcycle to its nominal value
* and phase_tracking=1.
* Enable phase accumulator clearing prior to programming.
*/
void dds_program(long long int timestamp, int channel,
int ftw, int pow, long long int phase_per_microcycle,
unsigned int ftw, unsigned int pow, unsigned int sysclk_per_microcycle,
int rt_fud, int phase_tracking)
{
long long int fud_time;
long long int phase_time_offset;
unsigned int phase_time_offset;

rtio_fud_sync();
DDS_WRITE(DDS_GPIO, channel);
@@ -71,9 +71,10 @@ void dds_program(long long int timestamp, int channel,
fud_time = timestamp;
else {
fud_time = rtio_get_counter() + 8000;
/* POW is mod 2**14, so wraparound on negative values is OK */
phase_time_offset -= timestamp - fud_time;
}
pow += phase_time_offset*phase_per_microcycle;
pow += phase_time_offset*ftw*sysclk_per_microcycle >> 18;
DDS_WRITE(DDS_POW0, pow & 0xff);
DDS_WRITE(DDS_POW1, (pow >> 8) & 0x3f);

2 changes: 1 addition & 1 deletion soc/runtime/dds.h
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@
void dds_init(void);
void dds_phase_clear_en(int channel, int phase_clear_en);
void dds_program(long long int timestamp, int channel,
int ftw, int pow, long long int phase_per_microcycle,
unsigned int ftw, unsigned int pow, unsigned int sysclk_per_microcycle,
int rt_fud, int phase_tracking);

#endif /* __DDS_H */
4 changes: 3 additions & 1 deletion test/serialization.py
Original file line number Diff line number Diff line change
@@ -4,12 +4,14 @@

import numpy as np

from artiq.language.units import *
from artiq.management import pyon


_pyon_test_object = {
(1, 2): [(3, 4.2), (2, )],
Fraction(3, 4): np.linspace(5, 10, 1)
Fraction(3, 4): np.linspace(5, 10, 1),
"frequency": 10*GHz
}